1. Field of the Invention
The present invention relates to electronic circuits and, in particular, to calibrating a phase-locked loop incorporating multiple oscillators.
2. Description of the Related Art
A phase-locked loop (PLL) is widely used in communications systems for clock synthesis and generation. The PLL is a closed-loop frequency-control system based on the phase difference between the input clock signal and the feedback output signal of a controlled oscillator. FIG. 1 shows a typical PLL, PLL 100, having phase frequency detector (PFD) 102, charge pump 104, loop filter 106, tunable oscillator 108, and frequency divider 110. PLL 100 provides an output frequency signal based upon an input reference frequency signal. Phase detector 102 compares the phase of the output frequency (or a divided-down output frequency) to the reference frequency to generate a phase error signal corresponding to the difference between the reference frequency and the output frequency. The phase error signal from phase detector 102 is used to adjust the frequency of oscillator 108, by causing charge pump 104 to either pump current to, or sink current from, loop filter 106 based on the phase error signal. Loop filter 106 might be employed to smooth the output current from charge pump 104, and, if tunable oscillator 108 is a voltage controlled oscillator (VCO), loop filter 106 might also convert the output current, ICP, of charge pump 104 to an input voltage to oscillator 108. This feedback loop generated control signal applied to oscillator 108 allows PLL 100 to keep the phases of the reference frequency and the output frequency matched, which allows PLL 100 to closely track the input frequency, or to generate a frequency that is a multiple of the input frequency when frequency division by frequency divider 110 is employed in the feedback loop.
The frequency range of oscillation of oscillator 108 directly determines the top and bottom oscillation rates of PLL 100. A common application of a PLL is in a serializer-deserializer (SERDES) device, and the range of standard clock signals a SERDES device can support, and its performance, is fundamental to the performance of the overall system employing the SERDES device. The top oscillation frequency, Rj and Pj levels (random and periodic jitter levels, respectively), tuning range (range of oscillation frequencies), and start-up margin are key performance measures for a PLL.
For the PLL of FIG. 1, a complimentary cross-coupled LCVCO architecture might be employed for oscillator 108, such as shown in FIG. 2. In general, a complimentary cross-coupled LCVCO might be suitable for system-on-chip (SoC) applications. LCVCO 108 comprises a cross-coupled differential amplifier 202 with an LC tank in its feedback path. This LC tank is composed of inductance provided by inductor 204 (with exemplary inductive value L1) and a capacitance provided by parallel-coupled varactors 208 (with exemplary capacitive values Var1) and switched capacitor banks 206 (with exemplary capacitive values C1). Switched capacitor banks 206 are optionally included to extend the tuning range of the VCO, for example by selecting a given tuning curve of the VCO. The VCO oscillates as given in equation (1):ωosc={L·(Ctran+Cloud+Creg+Csweap+Cvar)}−1/2  (1)where L is the inductance, Ctran and Cloud are the loadings from the negative gm transistors of the differential amplifier and the following stage circuitry, Creg is the circuit's routing and parasitic capacitance for the implementation, Csweap is the switched-capacitor bank capacitance, and Cvar is the varactor capacitance.
Implementing a wide-tuning range PLL is difficult for deep-submicron standard CMOS technology with high gate and channel leakage, such as 40 nm geometry CMOS technology integrated circuit (IC) chips. Further, the precise control of the target control voltage, Vtune, is important for setting the PLL to overcome a significant amount of PVT variations and balancing between random and periodic jitter performances. PLL VCO calibration might be performed during an initialization or reset of the PLL. PLL VCO calibration might be employed to select a given tuning curve of the VCO, for example using switched capacitor banks 206. Thus, the particular tuning curve chosen might need to tolerate PVT variation while maintaining acceptable PLL performance in the time between being chosen and a next reset of the PLL. Two distinct methods are commonly employed for automatic tuning of the frequency of LCVCOs: (i) open-loop calibration, and (ii) closed-loop calibration. A fundamental problem with open-loop calibration is that it requires breaking of the PLL loop and forcing an external voltage onto the sensitive Vtune control line. After calibration, although those calibration circuits are disabled, leakage paths might still exist, and disturbance and resulting jitter might be introduced.
In prior-art closed-loop calibration, the control voltage of the PLL is compared with two fixed voltages: an upper threshold voltage and a lower threshold voltage. These comparisons determine whether the frequency of the VCO is in range, or has to be increased or decreased. To ensure PLL frequency range, the two fixed thresholds are usually defined by the extremes of the allowable Vtune voltage range (e.g., a maximum Vtune value and a minimum Vtune value), such as shown in FIG. 4. As shown in FIG. 4, one or more tuning curves 302(1)-302(N) might fall within a window of output frequency operation of the PLL, as indicated by dashed lines Vtune(min), Vtune(max), fo,min and fo,max. The maximum and minimum levels of Vtune might be determined by the characteristics of charge pump 104, for example when charge pump 104 enters the triode region of operation, as shown in FIG. 4. A fundamental problem with previous closed-loop calibration is that the threshold voltages are pre-set and fixed before calibration starts. In addition, these preset thresholds are usually at the operating voltage extremes in order to achieve the maximum possible frequency range of the PLL. Thus, as shown in FIG. 4, with the closed-loop calibration of the prior art, a fixed Vtune minimum and a fixed Vtune maximum are chosen as calibration lower and upper thresholds. As shown, these thresholds are typically chosen at the edge of the functional operation region to ensure frequency locking range in the uncertainty of VCO frequency-band overlap from the device modeling and extraction limitations during the design phase.
As shown in FIG. 5A, significant leakage current from the Vtune node might increase in deep submicron poly-gate CMOS technology, such as 40 nm TSMC CMOS technology, as technology geometries decrease in size. This leakage current might lead to periodic jitter of the PLL output. As shown in FIG. 5A, gate leakage from 0.9V 40 nm varactor is shown to be higher than 65 nm and 90 nm devices.
A fundamental problem with the previous art close-loop calibration method is that the threshold voltages are preset and fixed before the calibration starts. In addition, these preset thresholds are typically extreme voltages to ensure the operating frequency range of the PLL. Further, as shown in FIG. 5B, there is uncertainty of VCO frequency-band overlap from the device modeling and extraction limitations during the design phase. As a result, the frequency band chosen for a certain frequency at the end of the calibration is arbitrary, and highly depends on the initialized value when the calibration starts, no matter how well the underlying PLL circuit actually performs. Therefore, although a frequency might be well in the operating range of the PLL, and there are frequency bands available to offer that frequency with centered Vtune voltages, the calibration engine might choose a frequency band that requires an extreme Vtune voltage. Consequently, selecting a tuning curve near a maximum or minimum operating voltage of Vtune provides little flexibility in adjusting Vtune to compensate for PVT variations, leading to higher random and periodic jitter of the PLL.